RobustPCBWhere Robust Design Starts
الحاسباتEnglishUpgradeتسجيل الدخولإنشاء حساب

ما الجديد

سجل التغييرات الكاملالمحرّك 1.26.4

Input EMI Filter & Damping

Protection & EMC

Is the input filter quiet enough, and will it stay stable with the converter behind it?

هذه الصفحة غير مترجمة بالكامل بعد. الأجزاء غير المترجمة معروضة بالإنجليزية.

المدخلات

The lowest input sets the smallest |ZN| (Kollman).
V
Pout / η at full load.
W
Hz
400 kHz
From your conducted-emission budget.
dB
H
2.2 µH
Inductor datasheet, at your hottest temperature.
A
The value left after DC bias at Vin (MLCC Effective Capacitance).
F
10 µF
2 to 10 is usual (MIT 6.622). A larger n gives a lower peak but needs a bigger Cd.
DCR, ESR and ESL
Inductor datasheet.
Ω
20 mΩ
Capacitor datasheet, near fc.
Ω
5 mΩ
Capacitor datasheet, plus pads and vias.
H
1 nH
Loop crossover
From the converter datasheet or your loop design. Blank assumes it is above 3 × the damped peak.
Hz

النتائج

Stability margin M
35.97dB
ناجح

المعيار: M ≥ 12 dB (design margin), failing below 6 dB (Kollman, Power Tip #4); checks |ZN| = Vin²/Pin, not ZD; with DCR 20 mΩ, ESR 5 mΩ, ESL 1 nH; assumes crossover above 66.4 kHz
أظهر خطوات الحساب
  1. Filter cornerf_c = 1 / (2π√(L_f × C_f)) = 1 / (2π√(2.2 µH × 10 µF)) = 33.93 kHz
  2. Converter input impedance|Z_N| = V_in² / P_in = 24² / 26.7 = 21.57 Ω
  3. Damping resistorR_d = Z_0 × √((2 + n)(4 + 3n) / (2n²(4 + n))) = 0.4690 Ω × √(6 × 16 / (2 × 16 × 8)) = 0.2872 Ω, nearest E24 0.30 Ω
  4. Stability marginM = 20 × log10(|Z_N| / peak |Z_out|) = 20 × log10(21.57 Ω / 0.3432 Ω) = 35.97 dB
Attenuation at fsw A(fsw)
43.53dB
Damping leg Rd+Cd

Rd to the nearest E24 value, Cd up to the next E12 value
0.30Ω + 47µF
Inductor current Iin
1.113A
كل النتائج (12)
Filter corner fc
33.93kHz
Characteristic impedance Z0
469mΩ
Converter input impedance |ZN|

Vin² / Pin, at the lowest input and full power
21.57Ω
Damped peak |Zout|

at 22.13 kHz
343.2mΩ
Undamped peak 

at 33.92 kHz, without the damping leg
8.804Ω
Undamped margin 

without the damping leg
7.784dB
Filter Q Q

Z0 / (DCR + ESR)
18.76
Rd before rounding Rd

the Erickson and Maksimović optimum
287.2mΩ
Cd before rounding Cd

n × Cf
40µF
Closed-form peak 

34.50 dB of margin, lossless and before rounding
406.2mΩ
Ideal attenuation Aideal

40 log10(fsw / fc)
42.86dB
Capacitor self-resonance fSRF

3.98 × fsw
1.592MHz
dampedundamped

إلى أي حد نعرف هذا الرقم

من أين تأتي الطريقة
  • Erickson and Maksimović
  • Perreault

Erickson and Maksimović, Fundamentals of Power Electronics المعادلة

Perreault, MIT 6.622 Power Electronics, input-filter damping المعادلة

يُقاس مقابل: Middlebrook, Design Techniques for Preventing Input-Filter Oscillations in Switched-Mode Regulators, as cited by Kollman and by Erickson and Maksimović; Kollman, TI Power Tip #4, Damping an input filter, part 2

مدى دقتها
Exact small-signal arithmetic on a lumped model: L_f with its DCR, C_f with its ESR and ESL, and the rounded damping leg, fed from a zero source impedance.

The converter is taken as the constant-power load −V_in²/P_in, which holds only well below its loop crossover. The C_f left after DC bias usually dominates the answer.

عملياً يهيمن على عدم اليقين مدخل واحد: Filter capacitance (effective). ضيّقه يضِق معه الجواب.

يُقاس مقابل

2 حالات في هذا الموقع تقارن هذه الحاسبة بأرقام حُسبت من دون كودها. اطّلع على الحساب.

هذه أداة مساعدة للتصميم. يبقى المهندس مسؤولاً عن التصميم وعن قراءة المرجع القياسي نفسه حيث يهم ذلك.

المسح البارامتري

غيّر مدخلاً واحداً على مدى، وشاهد الإجابة والحكم والهامش عند كل خطوة، جدولاً ومنحنى.Pro

أسوأ الحالات

أضف التفاوتات إلى المدخلات لتحصل على النطاق المضمون حول الإجابة الاسمية، لا الحالة النموذجية وحدها.Pro

Parts that track move together.القطع من النوع والتفاوت نفسه تتحرك معاً، كمصفوفة متوافقة أو بكرة واحدة، بدل أن تتحرك مستقلة.

Circuit

المبدأ

A switching converter that regulates its output draws constant power, so well below its loop crossover its input behaves as a negative resistance, −Vin²/Pin. The LC filter in front of it has a resonant peak in its output impedance. When that peak comes near the converter's input impedance, filter and converter can oscillate together (Middlebrook). This page checks the filter's attenuation at fsw, sizes an Rd–Cd damping leg across Cf, and compares the damped peak with |ZN| at the lowest input and full power.

Corner and characteristic impedance
fc=12πLf CfZ0=LfCfQ=Z0DCR+ESRf_c = \frac{1}{2\pi\sqrt{L_f\, C_f}} \qquad Z_0 = \sqrt{\frac{L_f}{C_f}} \qquad Q = \frac{Z_0}{\t{DCR} + \t{ESR}}
Taking Q from the series losses alone is a design simplification. With DCR + ESR = 0, Q and the undamped peak are unbounded.
Converter input impedance (−V²/P)
ZN≈−Vin2Pin∣ZN∣min=Vin,min2Pin,maxZ_N \approx -\frac{V_{in}^{2}}{P_{in}} \qquad |Z_N|_{min} = \frac{V_{in,min}^{2}}{P_{in,max}}
Well below its loop crossover a regulating converter holds its input power constant, so its input looks like a negative resistance (Erickson and Maksimović). The lowest input and the highest power give the smallest |ZN| (Kollman, Power Tip #4).
Optimum damping resistor and C_d
Rd=Z0(2+n)(4+3n)2n2(4+n)Cd=n CfR_d = Z_0\sqrt{\frac{(2+n)(4+3n)}{2n^{2}(4+n)}} \qquad C_d = n\, C_f
Erickson and Maksimović, parallel Rf–Cb damping. The page rounds Rd to the nearest E24 value and Cd up to the next E12 value, a design choice.
Peak output impedance at the optimum
∥Zout∥mm=Z0 2(2+n)n\left\| Z_{out} \right\|_{mm} = Z_0\, \frac{\sqrt{2(2+n)}}{n}
Erickson and Maksimović, for a lossless Lf and Cf. The page also finds the peak numerically, with the rounded parts, the DCR, the ESR and the ESL, and judges that one.
Stability margin
M=20log⁡10∣ZN∣max⁡f∣Zout(f)∣Zout=ZL∥ZC∥ZlegM = 20\log_{10}\frac{|Z_N|}{\max_f |Z_{out}(f)|} \qquad Z_{out} = Z_L \parallel Z_C \parallel Z_{leg}
Middlebrook's condition is |Zout| ≪ |ZN| and |Zout| ≪ |ZD|. The page checks ZN only. Kollman gives 6 dB as the minimum; 12 dB is this page's design margin.
Attenuation
A(fsw)=−20log⁡10∣ZshZL+Zsh∣Zsh=ZC∥ZlegAideal=40log⁡10fswfcA(f_{sw}) = -20\log_{10}\left|\frac{Z_{sh}}{Z_L + Z_{sh}}\right| \qquad Z_{sh} = Z_C \parallel Z_{leg} \qquad A_{ideal} = 40\log_{10}\frac{f_{sw}}{f_c}
From a zero source impedance, a design choice. ZL = DCR + jωLf, ZC = ESR + jωESL + 1/(jωCf), Zleg = Rd + 1/(jωCd).
Filter inductor for the target
fc,t=fsw 10−(At+6)/40Lf=1(2πfc,t)2 Cff_{c,t} = f_{sw}\, 10^{-(A_t + 6)/40} \qquad L_f = \frac{1}{(2\pi f_{c,t})^{2}\, C_f}
The ideal LC roll-off meeting your target plus 6 dB at fsw: the rule the "Lf for the target" mode uses, a design choice.
Capacitor self-resonance
fSRF=12πESL Cff_{SRF} = \frac{1}{2\pi\sqrt{\t{ESL}\, C_f}}
Above fSRF the capacitor is inductive and the attenuation stops rising.
  • fcf_cfilter corner, Lf with Cf
  • Z0Z_0characteristic impedance of the filter
  • QQfilter Q from the series losses
  • nnCd / Cf, the damping capacitor over the filter capacitor
  • Rd, CdR_d,\,C_ddamping leg across Cf
  • ZNZ_Nconverter input impedance with the output held by its loop: −Vin²/Pin, well below crossover
  • ZDZ_Dconverter input impedance with the duty cycle held
  • ZoutZ_{out}filter output impedance, seen from the converter
  • ZshZ_{sh}shunt branch: Cf and the damping leg in parallel
  • AtA_tyour required attenuation at fsw
  • MMstability margin
  • fSRFf_{SRF}self-resonant frequency of Cf with its ESL
  • DCR, ESR, ESL\t{DCR},\,\t{ESR},\,\t{ESL}inductor resistance; capacitor resistance and inductance
تفاصيل إضافية

Why a damping leg

An LC filter with low losses peaks at about Q × Z0 near fc. A resistor across Cf alone would damp it, but with the DC input across it, it would dissipate power all the time. In series with a blocking capacitor Cd it damps the peak and carries no DC. A larger n gives a lower peak, but a bigger Cd (Erickson and Maksimović).

Not modelled

ZD, the source's own impedance (taken as zero), the converter's input capacitance, Cd's own ESR and ESL (the leg is taken as an ideal Rd and Cd), and the ripple current in Cd. Above the loop crossover the converter's input is no longer −Vin²/Pin; enter the crossover to have the page check that the damped peak sits well below it.

Check the margin at the lowest input and full power, with the Cf left after DC bias.
References: R. Erickson and D. Maksimović, Fundamentals of Power Electronics: optimum parallel Rf–Cb damping, its peak output impedance, and the impedance inequalities. R. D. Middlebrook, Design Techniques for Preventing Input-Filter Oscillations in Switched-Mode Regulators, as cited by Kollman and by Erickson and Maksimović. R. Kollman, TI Power Tip #4, Damping an input filter, part 2: the minimum input impedance Vin,min²/Pmax and the 6 dB minimum. D. Perreault, MIT 6.622 Power Electronics, input-filter damping. Related: Buck Converter Design, Boost Converter Design, MLCC Effective Capacitance.

إصدار المحرك ⁨1.26.4⁩